A three-dimensional memory device including a three-dimensional vertical NAND strings having one bit per cell is disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. Support circuitry for performing write, read, and erase operations of the memory cells in the vertical NAND strings typically are provided by complementary metal oxide semiconductor (CMOS) devices formed on a same substrate as the three-dimensional memory device. using